1. Field of the Invention
The invention pertains to semiconductor processing methods and semiconductor constructions. In particular aspects, the invention pertains to a method and apparatus to integrate and fabricate coplanar void-isolated regions of different semiconductor materials on a hybrid monolithic substrate.
2. Description of Related Art
The need for semiconductor substrates having regions of multiple crystal orientations (e.g., <100> versus <110> versus <111>), or regions of a mixture of silicon-on-insulator (SOI) and bulk, or regions of different semiconductor type materials (e.g., Si or Ge type IV versus compound semiconductor materials) is well recognized by persons skilled in the art of semiconductor industry.
With respect to substrates having multiple crystal orientations, NFETs benefit from increased electron mobility in <100> oriented substrates while PFETs are observed to have increased hole mobility in <110> oriented substrates. The hole mobility was reported to be double in <110> oriented substrates relative to <100> oriented substrates. Further, in such multiple crystal orientation substrates, it is undesirable to have all the regions to be bulk substrates or SOI substrates. Bulk and SOI substrates each have preferred product applications. For example, SOI substrates provide reduced junction capacitance, dynamic threshold voltage (V.sub.t), and drain current enhancement due to gate to body coupling, and such properties are desired for high performance CMOS applications.
However, floating body effects of SOI substrates can result in unacceptable leakage currents and data retention problems for DRAM semiconductor types.
There is a further need for substrates having regions of different semiconductor material types. Semiconductor devices fabricated on silicon (group IV) substrates are abundantly employed in high-volume low-cost microelectronics where high-density, high-performance, and low-power consumption are simultaneously desired. CMOS, bipolar, and BICMOS technologies fabricated on either bulk silicon or silicon on insulator (SOI) substrates are commonly used in microprocessor, memory, and analog electronics applications.
Optoelectronic devices that are commonly used include III-V and II-VI compound semiconductor materials such as GaAs, InP, InGaP, InAs, AlGaAs, GaN, GaInAs, and AlGaSb. These compound semiconductor materials possess direct band gap properties and high photo-emission efficiency. Further, electronic properties of compound semiconductor materials make them ideal candidates for optoelectronics products such as LEDs, VCELs, photovoltaic devices, as well as high performance microwave devices such as PIN diodes, and heterojunction bipolar transistors (HBTs). Thus, semiconductor substrates having a mixture of group IV semiconductor material and compound semiconductor material are highly desirable.
Designers, however, face persistent problems in integrating electronic and optoelectronic devices from multiple types of semiconductor materials into a single compact, high-performance and cost effective package. One such problem encountered by hybrid substrates as noted above is a high density of stress induced semiconductor crystal defects related to the fabrication process. Particularly, the epitaxial growth process used to form substrates of the hybrid type result in adjacent semiconductor regions having different coefficients of thermal expansion or different oxidation properties. During the course of subsequent processing, compressive stresses may develop in the hybrid substrate structure which can result in crystal dislocations.
Therefore, there is a need to overcome the above-noted problems to produce hybrid substrates having reduced concentration of crystal defects.